A Parallel FPGA Implementation of the Discrete Wavelet Transform Based on Polyphase Decomposition and Distributed Arithmetic Techniques

Ali Al-Haj


ASIC hardware implementations of the discrete wavelet transform are required to cope with the intensive real-time computations of the wavelet transform. In this paper, we describe a parallel implementation of the wavelet transform using one type of programmable Application Specific Integrated Circuits (ASICs); Filed Programmable Gate Arrays (FPGAs). The implementation is based on reformulating the discrete wavelet transform using the distributed arithmetic and ployphase decomposition techniques, so that the ample inherent parallelism of the transform can be well exploited by the fine-grained parallel architecture of Virtex FPGAs. The implementation is simple, scalable, and performs both the forward and inverse discrete wavelet transforms. Performance results demonstrate the applicability of FPGAs with the distributed arithmetic and ployphase decomposition techniques to achieve the required high computational speeds of the discrete wavelet transform.


Discrete Wavelet Transform, Mallat's Pyramid Algorithm, FPGA Virtex Devices, Polyphase Decomposition, Distributed Arithmetic, Parallel Implementation

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