A PC-Based Algorithm for Testing a Configured PLD Using Boundary Scan Test

Bashar S. Mohamad-Ali, Ziyad K. Farej

Abstract


A comprehensive algorithm, and a data structure are proposed to test configured programmable logic devices (PLD) through JTAG port (IEEE 1149.1) using boundary scan testing (BST). An exhaustive test vectors set (all possible logic combinations of inputs) is used to test any configured combination logic circuit, so that all possible stuck-at faults are covered. The correct response is stored either from a good configured PLD or from a simulation file. Then the actual response of an PLD is compared to the correct response, which is stored previously. The only limitation to such algorithm is the test time, which is increased exponentially with the number of inputs. This algorithm can be implemented using either a low level language (Assembly language) or a high level language (Visual C, Visual BASIC) on any personal computer via its printer port.


Keywords


PLD Testing, Test Algorithms, Boundary Scan Test.

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